Qualcomm will license patents behind Huawei’s LogicFolding chip architecture, report says

What happened

Qualcomm has entered into a cross-licensing deal with Huawei to access patents related to the LogicFolding chip-stacking technology. This technology, used in the Kirin 9050 Pro, involves splitting chip components across two bonded dies to enhance performance and efficiency. The deal covers various technologies, including 5G, AI, and networking, and is pending regulatory approvals.

Why it matters

The licensing of LogicFolding technology by Qualcomm highlights the importance of advanced chip-stacking methods in improving data transmission and energy efficiency. It also underscores the strategic importance of patent cross-licensing in the semiconductor industry, particularly for companies navigating regulatory and technological challenges.

• Qualcomm's licensing of Huawei's LogicFolding technology highlights the growing importance of chip-stacking methods in semiconductor design.
• Patent cross-licensing agreements are crucial for companies to navigate regulatory and technological challenges in the industry.
• Advanced chip-stacking techniques like LogicFolding can lead to significant improvements in energy efficiency and data transmission.

The bigger picture

The deal between Qualcomm and Huawei could influence the development of future chip technologies, particularly in areas like 5G, AI, and networking. It may also set a precedent for patent cross-licensing agreements in the semiconductor industry, affecting how companies collaborate and innovate.

Qualcomm's licensing of Huawei's LogicFolding patents marks a significant development in the semiconductor industry, emphasizing the role of advanced chip-stacking technologies in improving performance and efficiency. The deal, pending regulatory approvals, could influence future innovations and collaborations in 5G, AI, and networking.

Technical details

• LogicFolding: A chip-stacking method that splits components across two bonded dies to reduce signal paths and energy consumption.
• Hybrid bonding: Copper-to-copper bonding used to connect the two dies in the Kirin 9050 Pro.
• Through-silicon vias (TSVs): 80,000 TSVs in the lower die of the Kirin 9050 Pro, contributing to the chip's interconnect density.
• Tau Scaling Law: Huawei's approach using signal delay instead of transistor size as a measure for chip scaling.
• 3D V-Cache: AMD's 3D stacking technology for L3 SRAM, similar to Huawei's approach but with different specifications.

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